1. Field of the Invention
The present invention relates in general to a sense amplifier used to read data from a cell of a static random access memory (SRAM), and more particularly to a sense amplifier which is stably operated at a high speed with low power consumption.
2. Description of the Prior Art
Generally, in order to read data from a cell of an SRAM, a sense amplifier senses and amplifies two signals from bit and bit bar lines connected to the memory cell. The bit line is active high, whereas the bit bar line is active low.
Referring to FIG. 1, there is shown a circuit diagram of an SRAM to which a conventional sense amplifier is applied. In this drawing, the reference numeral 11 designates a cell, 12 a bit line, 12' a bit bar line, 13 a word line, 14 a pull-up circuit, 15 a transfer gate circuit, 16 a cell data bus line, 16' a cell data bus bar line, 17 an enable signal SAE supply line, 18 and 18' a pair of current mirror-type sense amplification circuits, and 19 a voltage sense amplification circuit, respectively.
When the bit and bit bar lines 12 and 12' are operated in the neighborhood of a supply voltage by PMOS transistors of the pull-up circuit 14, the operated voltages are transferred to the data bus and data bus bar lines 16 and 16' through the transfer gate circuit 15 and then to gates of NMOS transistors N11, N12, N14 and N15 of the pair of current mirror-type sense amplification circuits 18 and 18'. The transferred voltages are primarily amplified by the pair of current mirror-type sense amplification circuits 18 and 18' and secondarily by the voltage sense amplification circuit 19. As a result, the voltage sense amplification circuit 19 provides the amplified final output Sout.
Noticeably, provided that NMOS transistors are used in the pull-up circuit 14 instead of the PMOS transistors, consumption of threshold voltages thereof cause a voltage reduction. To prevent such a voltage reduction, the PMOS transistors are used in the pull-up circuit 14 with no use of the NMOS transistors. Namely, if the SRAM is pulled up by the NMOS transistors, the voltage reduction occurs due to the consumption of the threshold voltages of the NMOS transistors. This voltage reduction is not applicable to the SRAM requiring low power.
FIG. 2 is a graph illustrating an operating characteristic of the conventional sense amplifier in FIG. 1. As shown in this drawing, the supply voltage is decreased from 5 V (lines A) to 3.3 V (lines B) by the PMOS transistors of the pull-up circuit, thereby causing the final output Sout from the sense amplifier to have a gain (line C') smaller than that (line C) of 5 V and a long delay time. As a result, a voltage gain characteristic of the sense amplifier becomes unstable. To solve this problem, there must be used an additional address transition detection (ATD) circuit to generate an equalize pulse. The use of the additional ATD circuit results in an increase in the power consumption.